1. Field of the Invention
The present invention relates to current mirror circuits, and in particular, to metal oxide semiconductor field effect transistor (MOSFET) cascode current mirror circuits.
2. Description of the Related Art
Current mirror circuits, in general, are well-known in the art and are used in many applications. As is well-known, in a conventional current mirror circuit, an input current source drives one of a pair of transistors interconnected in such a manner that such input current is substantially replicated, or mirrored, at the output of the second transistor. As is also well-known, the relative sizes, or scaling, of the respective transistor dimensions can be designed to establish the desired ratio between the input current and the output, or mirrored, current. Accordingly, one important factor in designing such a current mirror circuit is matching the input and output currents according to the desired proportion or ratio.
Current mirror circuits found in present day integrated circuits (ICs) tend to be implemented using MOSFETs. As ICs have become increasingly dense, in terms of transistor count versus die size, channel lengths of the MOSFETs have also become shorter. Such decreased channel lengths result in decreased output impedances for current mirror circuits. Accordingly, it has become increasingly necessary to provide cascode output circuits to maintain or increase output impedances.
Cascode output stages often exhibit limited voltage ranges in terms of possible biasing voltage for the cascode output stage, as well as possible power supply voltages. With respect to possible power supply voltages, this has become increasingly critical as operating power supply voltages have decreased to 3.3 volts and below.
Referring to FIG. 1, for example, a conventional MOSFET cascode current mirror circuit 10 intended to provide an output current IOUT with an associated output voltage having a high dynamic range relative to its power supply voltage, while also operating with a minimum power supply voltage VDD (relative to the circuit reference or ground potential VSS/GND) is implemented using reference current sources 12, 14 and N-MOSFETs M1, M2, M3, M4, M5, M10, M11, all interconnected substantially as shown. (The reference current sources, 12, 14 can be implemented in a number of well-known ways such that the operating voltage across each current source 12, 14, when implemented with MOSFETs, is equal to the drain-to-source saturation voltage VDSAT.)
Diode-connected transistor M1, driven by current source 14, establishes a bias voltage V10 at the gate terminal of transistor M2. In turn, transistor M2 sinks the current provided by current source 12 and provides a bias voltage V3 at the gate terminal of transistor M3. The current through transistor M3 drives diode-connected transistor M5 as the input to a current mirror circuit formed by transistors M5 and M4. This biasing arrangement results in the equal reference current IREF of current sources 12 and 14 to be mirrored as the channel currents through transistors M3 and M5, and establishing the biasing voltages V10, V11 for the gate terminals of output transistors M10 and M11. Cascode output transistor M10 helps maintain a high output impedance for the output current IOUT at its drain terminal.
Transistors M2 and M4 serve as reference devices in helping to establish the mirrored current and biasing voltages V10, V11. Transistor M1 has a channel width (e.g., 4 microns) which is approximately equal to or less than the channel widths of the reference M2, M4 and output M10, M11 transistors (e.g., 20 microns) so as to maintain the minimum biasing potential for the output transistors M10, M11 (discussed in more detail below). The source follower configuration of transistors M3 and M5 establish the minimum power supply voltage (VDD−VSS/GND) as the sum of two threshold voltages VT (the minimum gate-to-source voltage VGS at which an inversion layer is formed and channel conduction, and therefore drain current flow, begins) plus one MOSFET drain-to-source saturation voltage VDSAT (2*VT+VDSAT).
As power supply voltages continue to decrease, it would be desirable to have a minimum operating power supply voltage less than that offered by the circuit of FIG. 1. Further, it would be desirable to accomplish this without requiring a second current source to generate the biasing voltage for the cascode output transistor.